1. Field of the Invention
The present invention relates to a digital code conversion apparatus, and more particularly, to an encoding or decoding apparatus capable of processing a digital code in a parallel manner.
2. Description of the Prior Art
Conventionally, when a digitally encoded video signal or the like is recorded or reproduced on a digital code record/reproduction apparatus such as a digital VTR, it has been the practice, for recording the signal, to convert the signal into a desired signal format by using a digital code modulation circuit, and, for obtaining the original, digitally encoded video signal, the recorded signal is reproduced and converted by using a digital code demodulation circuit.
That is, an analog signal such as a video signal is sampled and sequentially encoded, for example, into eight-bit digital information and then processed by a parallel-to-serial conversion circuit to be turned into serial data in synchronism with a predetermined clock signal.
Then, modulated data in the NRZ (non return to zero) modulation format, in which the logical level is inverted corresponding to the logical level of the aforesaid serial data, is obtained and thereby NRZ data is provided.
Further, there is a modulation method MFM (modified frequency modulation) format which is used to obtain MFM data. According to this MFM format, when a bit cell of NRZ data is at a logical 0, the corresponding logical level is inverted at the timing of the rise of the clock signal only when the logical level of the cell of the NRZ data occurring one clock period prior thereto is at a logical 0 (hereinafter, this will be called the first condition), and when the logical level of a bit cell of the NRZ data is at a logical 1, the corresponding logical level is inverted at the timing of the fall of the clock signal, namely, at that time point in the center of one clock period of the clock signal (hereinafter, this will be called the second condition).
When the signal is recorded on a magnetic tape based upon MFM data, a recorded signal containing only a small quantity of low frequency components can be obtained even if there appears information at the same logical level continuously in the serial data, and also, demodulation is easily made without the need for recording the clock signal at the same time.
However, since the MFM data DM (FIG. 1(A)) contains a D.C. component (i.e. the digital sum value or DSV) as shown in FIG. 1, there has been a problem that, in the case of some video signals, the D.C. component is continuously accumulated and as a result a D.C. level SD (FIG. 1(B)) exhibits a large variation.
To solve the aforementioned problem, the digital code modulation circuit according to the M.sup.2 code (modified Miller) format which was proposed in U.S. Pat. No. 3,108,261 is used in digital VTRs, so that the D.C. level will not vary beyond a predetermined value.
That is, in this format, a third condition is provided in addition to the first and second conditions used in the modulation format of the MFM data DM. The third condition is such that, when bit cells of the NRZ data whose logical level is at a logical 1 continuously appear and if the number of continuing bit cells of the NRZ data at a logical 1 is an even number (hereinafter, this will be called the pattern C), transition, or inversion of the logical level of the last bit cell in the following bit cells at "1" is suppressed. This causes the directions of the transitions of the MFM data DM as a whole to be reversed so that the M.sup.2 data DMM (FIG. 1(D)) exhibiting a smaller variation in the DC level SD1 (FIG. 1(C)) can be obtained.
When modulating the NRZ data in such a digital code modulation circuit for the M.sup.2 data DMM, however, the modulation of each bit cell thereof has to be made based upon the logical levels of the bit cells of the NRZ data input previously and that of the NRZ data input following thereto. Further, in digital code demodulating such M.sup.2 data DMM, the signal must be demodulated into NRZ data by exclusive OR operations performed on two bits of the M.sup.2 data DMM, and at the same time, the presence or absence of the pattern C must be detected.
Therefore, in a conventional digital code modulation and demodulation circuit of this type, the input data is serially processed in succession. Hence, in the conventional digital code modulation and demodulation circuit for such M.sup.2 data DMM, the processing has to use a clock signal having a frequency twice as large as that of the clock signal of the NRZ data.
Since, in reality, the clock frequency of the NRZ data used in VTRs is high, it has been a problem that a clock signal of about 120 MHz, which is two times the frequency of the clock signal in the video signal in the NTSC system, or about 160 MHz in the case of the PAL system, must be used. Further, a clock signal of about 200 MHz is required for processing the NRZ data when special reproduction modes are taken into consideration.
When such a clock frequency is used, it becomes difficult to modulate the digital signal in a stable manner by the use of TTL (transistor transistor logic) and CMOS (complementary metal oxide semiconductor) integrated circuits as used in general logical circuits, and therefore, the digital code modulation and demodulation circuit in digital VTRs has until now been constructed, for example, of an ECL (emitter coupled logic) digital integrated circuit capable of high-speed switching.
But if such a construction is used, the power consumption in the digital calculating modulation circuit becomes great, and as a result it becomes difficult to achieve higher complexity in the integrated circuits. Thus, it has been inevitable that the digital VTR as a whole becomes larger in size, consuming more power, and hence more expensive.